Performance Analysis Of Dynamic Protocol Adaptation In Soc Architectures Using DRAM Model

Abstract

The proposed work presents a dynamic protocol adaptation framework within a System-on-Chip (SoC) architecture to improve energy efficiency and performance.It integrates components like processors and communication protocols (AXI, AHB, APB) essential for data transfer. The design features a Cortex-M33 processor and a Real-Time Monitoring System that evaluates workload and performance metrics for optimal communication protocol selection. The Protocol Adaptation Mechanism dynamically adjusts protocol settings, while the Protocol Configuration Manager facilitates transitions among various protocols. To ensure efficient data transfer, AXI-to-APB, and AHB-to-APB bridges are included. The DRAM module enhances memory performance with 1300-location depth.Results show significant improvements: for the 32-bit processor, slice register usage drops from 3201 to 3941, delay improves from 6 ns to 4.53 ns, and power consumption decreases from 17.34 mW to 11.96 mW. For the 64-bit processor, slice register usage declines from 4613 to 3991, delay improves from 13.45 ns to 8.35 ns, with power reduced from 15.34 mW to 11.42 mW. The area is also minimized, while throughput increases significantly. Validated through obtained results in Vivado Design Suite 2018.1 on the Zynq 7000 board with comprehensive testing, this framework demonstrates enhanced adaptability and efficiency for various applications.