Design And Analysis of Low-Noise Amplifiers for High-Speed Analog VLSI Applications

Abstract

Low-noise amplifiers (LNAs) constitute an vital part in contemporary high-speed analog VLSI circuits where noise suppression and gain tuning have direct implications on performance in wireless communications and high-frequency data processing. This work introduces the plan, simulation, and analysis of a CMOS-based amplifier designed to be optimized for high-speed analog VLSI applications. The target design combines current-reuse circuit techniques as well as the source-degeneration approaches to realize low noise figures and high linearity. The simulation results show a gain of 18.6 dB, noise figure of 2.1 dB, and power consumption of 4.5 mW at supply voltage of 1.2 V, making the design appropriate for future-generation high-speed analog systems. The results are confirmed with schematic simulation results and performance comparison against previous designs.