Cortex-M33-Based Soc Design With Optimized Dynamic Protocol Adaptation For Data Communication

Abstract

This paper investigates a dynamic protocol adaptation framework into a System-on-Chip (SoC) framework to enhance power consumption and performance, which contains such elements as processors and communication system (AXI, AHB, APB) inherent in data moving. It is designed by a Cortex-M33 processor and Real-Time Monitoring System to assess the workload and performance measures to determine an ideal selection of communication protocols. The Protocol Adaptation Mechanism dynamically adapts protocol parameters whereas Protocol Configuration Manager helps network movement between different protocols. The inclusion of AXI-to-APB, and AHB-to-APB bridges allow the transfer of data to work efficiently. The SRAM module increases the depth of the performance of memory to 1500-location. The results indicate significant improvement: in the case of the 32-bit processor, where the slice register usage is reduced to 3491 as compared to 4201, the delay is reduced to 4.35 ns as opposed to 7 ns, and the use of power decreases to 10.96 mW according to 18.34 mW. In the case of the 64-bit processor, we will get a reduction in using slice registers (4913 to 3891), improvement in delay (11.45 ns to 7.35 ns) and a decrease in power consumption (17.34 mW to 10.42 mW). The space is also reduced and the throughput is boosted greatly. This framework is verified by the results that were gained in Vivado Design Suite 2018.1 of Zynq 7000 board after full testing, showing greater versatility and effectiveness across different programs.