Implementation Of Low Power And High-Speed Adders Using Different Techniques

Abstract

Addition is an important operation among all the fundamental operations of calculations, used for many arithmetic and logical calculations. This project’s objective is to reduce power and delay by employing various techniques like CMOS design, TGFA (Transmission Gate Full Adder), SERF (Static Energy Recovery Full Adder) methods that are used for extending the battery life. Using different techniques of full adder, the 16-bit   Ripple Carry Adder (RCA) and 16-bit Carry Select Adder (CSA) designs are implemented. The timing parameters of each adder were first characterized. Comparing the conventional adders in various performances such as power consumption and speed. The adders’ designs are made and implemented using Tanner EDA v14.1 with 130nm and 90nm technologies.