Area and Delay Optimized 4×4 Dadda Multiplier Design in 45nm CMOS Technology
DOI:
https://doi.org/10.64252/4r2ydb59Keywords:
Dadda multiplier, 4-bit multiplier, low power, high speed, pass-transistor logic, CMOS 45nm, Vivado, ModelSim, Microwind, dynamic power, propagation delay, digital circuit designAbstract
This project presents a detailed model of a 4-bit multiplier emphasizing low power consumption and high-speed operation, achieved using the Dadda algorithm. The primary building block of this design is an optimized full adder, featuring low power dissipation and minimal propagation delay. To realize these characteristics, the full and half adder blocks are carefully designed using pass-transistor logic and implemented with 45nm CMOS process technology, significantly reducing both power consumption and delay. The application of the Dadda algorithm further enhances performance by minimizing propagation delay within the multiplier architecture.
The model has been developed using Vivado, ModelSim, DSCH, and Microwind tools, utilizing advanced 90nm technology for implementation. The proposed multiplier operates at a frequency of 3.83 GHz, demonstrating its high-speed performance. It also exhibits an average dynamic power consumption of 184.3 μW at a supply voltage of 1V. This efficient design results from the combination of innovative algorithmic techniques and advanced circuit design methodologies, ensuring both low power operation and high-speed performance.
