A Power-Efficient 32-Bit ALU Using 16 Nm Finfet Technology Based NCL Standard Cells For Asynchronous VLSI Systems
DOI:
https://doi.org/10.64252/386xw282Keywords:
Null Convention Logic (NCL), Asynchronous Design, FinFET, Threshold Logic Gates, Power-Delay Product, Standard Cell Library, ALU, Dual-Rail Logic, Completion DetectionAbstract
The need for low-power, high-speed computing in nanometer-scale technology nodes has driven innovation in asynchronous design paradigms. Null Convention Logic (NCL), a delay-insensitive asynchronous methodology, eliminates the global clock and enhances power efficiency. In this paper, we propose a novel 32-bit Arithmetic Logic Unit (ALU) designed using NCL standard cells implemented with 16nm FinFET technology. A complete library of 27 NCL threshold gates was developed and characterized using Cadence tools and the Synopsys ecosystem. The FinFET-based NCL gates show significant improvements in delay (up to 16.5%) and power (up to 7.2%) over static and semi-static CMOS equivalents. The ALU design leverages the robustness and energy benefits of NCL and FinFETs, and is validated through full custom layout, simulation, and performance benchmarking. The proposed design demonstrates promise for asynchronous embedded and low-power VLSI systems.
