"Dynamic Voltage Scaling For Low-Power VLSI Design: A Review Of Power Optimization Techniques And Memory Efficiency Enhancements"
DOI:
https://doi.org/10.64252/3pyf9k26Keywords:
1. Dynamic Voltage scaling 2. Power Gating 3.Clock Gating 4. Low Power Design 5. Power Manage- ment Techniques.Abstract
The increasing demand for energy efficient devices, from mobiles systems to high performance computing, has made VLSI design a crucial study topic. Battery life, heat dissipation, and overall system reliability are all directly impacted by power usage. Dynamic Voltage Scaling (DVS), one of the best power management strategies, dynamically modifies the supply voltage and significantly lower power usage without noticeably compromising performance in response to workload demands. By altering the operating voltage of a processor or circuit block in reaction to variations in workload. DVS aids in the optimization of both dynamic and leaky power. The system runs at a lower voltage while processing demands are minimal, but large computational loads cause the voltage to rise in order to sustain performance. This study reveals the various power management techniques and compares the performance to give suitable method for particular application. By decreasing voltage levels during idle times, DVS lowers standby power consumption in memory units and increase memory efficiency.
